Verilog Tutorial

Verilog Tutorial 1 Introduction There are several key reasons why we use hardware description languages (HDLs): • They give us a text-based way to describe and exchange designs. • They a way to simulate the operation of a circuit before we build it in silicon. It is usually easier to debug a model of the circuit rather than the real circuit in silicon. • With special tools we can automatically translate our Verilog models to the information needed for circuit implementation in silicon. This translation takes the form of partitioning and mapping to primitive circuit elements, element placement, and wire routing. The set of translation tools could also include logic synthesis—automatic generation of lower-level logic circuit designs from high-level specifications. Two standard HDLs are in wide use, VHDL and Verilog. We use Verilog because it is easier to learn and use for most people because it looks like the C language in syntax. Also, it is widely used in industry. Furthermore, because the semantics of both are very similar, making a switch to VHDL from Verilog later is not a problem. Verilog is a language that includes special features for circuit modeling and simulation. In this course, we will employ only a simple subset of Verilog. In fact, we will focus just on those language constructs used for “structural composition”—sometimes also referred to as “gate-level modeling”. These constructs allow us to instantiate primitive logic elements ...