Identify Actel Edition Quick Tutorial

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®Identify Actel Edition
Quick Tutorial
September 2010
http://solvnet.synopsys.com
Disclaimer of Warranty
Synopsys, Inc. makes no representations or warranties, either expressed or
implied, by or with respect to anything in this manual, and shall not be liable
for any implied warranties of merchantability or fitness for a particular
purpose of for any indirect, special or consequential damages.
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Copyright © 2010 Synopsys, Inc. All Rights Reserved.
Synopsys software products contain certain confidential information of
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or omissions. This publication and the features described herein are subject
to change without notice.
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2 Identify Actel Edition Quick Tutorial, September 2010
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Printed in the U.S.A
September 2010
Identify Actel Edition Quick Tutorial, September 2010 3
LO
4 Identify Actel Edition Quick Tutorial, September 2010Introduction
This simple tutorial teaches you how to instrument and debug a small HDL
design. The design is a simple 4-bit counter with a clock and reset. Two
versions of the counter are provided: one in VHDL and one in Verilog.
Note: This tutorial simulates hardware debug data by applying randomly
generated data to all instrumented nodes. This data does not reflect
the actual operation of the design and only serves to show the format
of the debug data.
Note: A more detailed tutorial, which can be used with actual hardware, is
included in the documentation set.
Identify Actel Edition Quick Tutorial Copyright © 2010 Synopsys, Inc.
September 2010 5Design Schematic
The following figure shows the simple state machine configured as a 4-bit
counter. The state diagram is shown to the left of the schematic.
State Machine
Schematic
Design Description
The tutorial design is implemented in Verilog as a single module with two
always block statements and in VHDL as a single entity with two processes.
The first always block (Verilog) or process (VHDL) implements a state machine;
the second always block or process computes the output values based on the
current state.
LO
Copyright © 2010 Synopsys, Inc. Identify Actel Edition Quick Tutorial
6 September 2010Instrumenting Your Design
Instrumenting Your Design
You use the Identify instrumentor to select both breakpoints and
watchpoints and to set the sampling and triggering modes. The
Identify instrumentor is launched from your Synplify Pro synthesis
tool and is run prior to synthesis.
Note: This tutorial describes running the Identify instrumentor from the
Synplify Pro tool. To run the Identify instrumentor in stand-alone
mode, see Chapter 3, Project Handling, in the user guide.
The HDL design and project files for this tutorial are included in a “tutorial”
subdirectory under the Identify software installation directory. Before you
begin the tutorial, copy the files to a local directory and make sure that you
have read and write permission for both the directory and files.
Note: While performing the tutorial, the active project (.prj) file will be
updated; copying the files to a local directory preserves the original
files installed in the tutorial directory.
To begin the instrumentation:
1. Start the Synplify Pro tool.
2. In the project view, click the Open Project button to display the Open
Project dialog box and click the Existing Project button.
3. Navigate to the tutorial directory where the Identify software is installed.
This directory includes the HDL design files and two Actel-specific
project files for Verilog and VHDL implementations.
4. Select (open) the appropriate project file.
Identify Actel Edition Quick Tutorial Copyright © 2010 Synopsys, Inc.
September 2010 7Instrumenting Your Design
5. Right click on the Identify implementation and select Launch Identify
Instrumentor from the popup menu.
6. If prompted, enter the location of the Identify installation in the Configure
Identify Launch dialog box, click the Locate Identify Installation radio button,
and click OK to launch the Identify instrumentor.
LO
Copyright © 2010 Synopsys, Inc. Identify Actel Edition Quick Tutorial
8 September 2010Instrumenting Your Design
7. If prompted for a license, select a license from the list of available
licenses displayed and click Select.
The following figure shows the initial Identify instrumentor window as
launched from the Synplify Pro tool on the Verilog version of the tutorial. The
window shows the design hierarchy on the left and the HDL file content with
all the potential instrumentation marked and available for selection on the
right.
Identify Actel Edition Quick Tutorial Copyright © 2010 Synopsys, Inc.
September 2010 9Instrumenting Your Design
Setting up the IICE
Click on the Edit IICE settings icon on the toolbar to bring up the IICE
Sampler tab shown in the following figure. The IICE Sampler tab defines
the sample depth, sampling modes, and the sample clock.
1. Leave Buffer type set to behavioral (only supported type)
2. Select 128 for the sample buffer depth.
3. Leave the Allow qualified sampling check box unchecked
4.Allow always-armed sampling check box unchecked
5. Enter /clk for the sample clock and select the positive polarity for the
clock edge.
6. After you have set and/or verified the above IICE Sampler tab settings,
LOclick the IICE Controller tab.
Copyright © 2010 Synopsys, Inc. Identify Actel Edition Quick Tutorial
10 September 2010