Rev September
Description
Rev. 1.5 - September 2002 1/84 PRELIMINARY DATASHEET ST52T410/T420/E420 8-BIT INTELLIGENT CONTROLLER UNIT (ICU) Three Timer/PWMs, ADC, WDG ? Memories Up to 4 Kbytes OTP 128 bytes of RAM Readout Protection Core Register File Based Architecture 55 instructions Hardware multiplication and division Decision Processor for the implementation of Fuzzy Logic algorithms Clock and Power Supply Up to 20 MHz clock frequency. Power Saving features Interrupts Up to 5 interrupt vectors Top Level External Interrupt (INT) I/O Ports 19 I/O PINs configurable in Input and Output mode High current sink/source in all pins. Peripherals 3 Programmable 8-bit Timer/PWMs with internal 16-bit Prescaler featuring: – PWM output – Input capture – Output compare – Pulse generator mode On-chip 8-bit Sample and Hold A/D Converter with 8-channel analog multiplexer (ST52T420/ E420 only) Watchdog timer Development tools High level Software tools Emulator Low cost Programmer Gang Programmer ST52T410/T420/ E420
- operational description
- emulator low cost
- configuration registers
- vpp pin
- global interrupt
- x8-bit
- eprom programming
- low power
Sujets
Informations
| Publié par | pefav |
| Nombre de lectures | 19 |
| Langue | English |
Extrait
Memories Up to 4 Kbytes OTP 128 bytes of RAM Readout Protection
SET42502T410/T420/ST52T410/T420/E420 8-BIT INTELLIGENT CONTROLLER UNIT (ICU) Three Timer/PWMs, ADC, WDG PRELIMINARY DATASHEET
Core Register File Based Architecture 55 instructions Hardware multiplication and division Decision Processor for the implementation of Fuzzy Logic algorithms
Clock and Power Supply Up to 20 MHz clock frequency. Power Saving features
Interrupts Up to 5 interrupt vectors Top Level External Interrupt (INT)
I/O Ports 19 I/O PINs configurable in Input and Output mode High current sink/source in all pins.
Peripherals Development tools 3 Programmable 8-bit Timer/PWMs with internal i h level Software tools 16-bitPrescalerfeaturing:HEmgultor a ± PWM ±InptoupttpuurteLowcostProgrammer ±OutupuctacompareGangProgrammer
± Pulse generator mode On-chip 8-bit Sample and Hold A/D Converter with 8-channel analog multiplexer (ST52T420/ E420 only) Watchdog timer
Rev. 1.5 - September 2002
1/84
Yes
2.7-5.5 V
1 9
3x8-bit
1 28
2K OTP
ST52T4 10G1py
-
Yes
3.0-5.5 V
1 9
8 -Ch
1 28
1K OTP
ST52T4 10G0py
-
Dip/So 2 8
Cdip 28
1 9
Dip/So 2 8
Dip/So 2 8
2/84
Dip/So 2 8
Dip/So 2 8
1 28 3x8-bit -
Yes
3x8-bit
-
2.7-5.5 V
1 9
Yes
2.7-5.5 V
Dip/So 2 8
ST52T410/T420/E420
ST52T4 10G2py
Package
1 9
4K OTP
3.0-5.5 V
I/ O
Yes
Operating Supply
-
Watchdog
8-Ch
SCI
ST52T4 20G2py
-
Yes
3.0-5.5 V
8 -Ch
3x8-bit
1 28
4K OTP
-
Yes
3.0-5.5 V
1 9
3x8-bit
1 28
4K EPROM
ST52E420G2D6
RAM
Time rs PWM
ADC
Device
3x8-bit
1 28
ST52T410/ST52x420 Device Summary
NVM
ST52T4 20G1py
2K OTP
1K OTP
ST52T4 20G0py
8 -Ch
1 9
1 28
3x8-bit
TABLE TENTS
OF
CON-
TABLE OF CONTENTS
ST52T410/T420/E420
1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
1.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.2.1 Memory Programming Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.2.2 Working mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.3 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2 INTERNAL ARCHITECTURE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.1 ST52T410/ST52x420 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.2 Control Unit and Data Processing Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.2.1 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.2.2 Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.3 Address Spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3.1 RAM and STACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3.2 Input Registers Bench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.3.3 Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.3.4 Output Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.4 Arithmetic Logic Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3 EPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.1 EPROM Programming Phase Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.1.1 EPROM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.1.2 EPROM Locking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.1.3 EPROM Writing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.1.4 EPROM Read/Verify Margin Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.1.5 Stand by Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.1.6 ID code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.2 Eprom Erasure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5
4.1 Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
4.2 Global Interrupt Request Enabling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.3 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.4 Interrupt Maskability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.5 Interrupt Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.6 Interrupts and Low power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.7 Interrupt RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
CLOCK, RESET & POWER SAVING MODE . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.1 System Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.2 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
5.3 Power Saving Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 5.3.1 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.3.2 Halt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3/84
ST52T410/T420/E420
6 FUZZY COMPUTATION (DP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7
8
37
6.1 Fuzzy Inference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.2 Fuzzyfication Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.3 Inference Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.4 Defuzzyfication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.5 Input Membership Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 6.6 Output Singleton . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 6.7 Fuzzy Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 7.2 Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.3 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.4 Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.5 I/O Port Configuration Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
A/D CONVERTER (ST52X420 ONLY) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
8.2 Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 8.2.1 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 8.2.2 Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 8.3 A/D Registers Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 9 WATCHDOG TIMER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
9.1 Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 9.2 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 10 PWM/TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 10.1 Timer Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 10.2 PWM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 10.3 Timer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 11 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 11.1 Parameter Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 11.1.1 Minimum and Maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 11.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 11.1.3 Typical curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 11.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 11.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 11.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 11.3 Recommended Operating Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
11.4 Supply Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
11.5 Clock and Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
11.6 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
11.7 ESD Pin Protection Strategy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
4/84
11.7.1 Standard Pin Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
11.7.2
Multi-supply Configuration
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.8 Port Pin Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ST52T410/T420/E420
. . . . . . . . . . . . .
. . . . . . . . . . . . .
. . . . 74
. . . . . 75
11.8.1 General Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
11.9 Control Pin Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
11.9.1 RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
11.9.2 VPP pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
11.10 8-bit A/D Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
ORDERING
INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
5/84
ST52T410/T420/E420
6/84
1 GENERAL DESCRIPTION
1.1 Introduction ST52T410/ST52x420 are 8-bit Intelligent Control Units (ICU) of t he ST Five Family, which can perform both boolean and fuzzy algorithms in an ef ficient manner, in order t o reach t he best performances that the two methodologies allow. S T 5 2 T 4 1 0 / S T 5 2 x 4 2 0 a r e p r o d u c e d b y S TMi croel ect roni cs u si ng t he re lia ble hi gh performance CMOS process, including integrated-on-chip peripherals that allow maximization of system reliability, decreasing system costs and minimizing the number of external components. The flexible I/O configuration of ST52x400/440 allows for an interface with a wide range of external devices, like D/A convert ers or power control devices. ST52T 410/ ST52x420 pins are configurable, allowing the user to set the input or output signals on each single pin. A hardware multiplier (8 bit by 8 bit with 16 bit result) and a divider (16 bit over 8 bit with 8 bit result and 8 bit remainder) are availabl e t o implement complex functions by using a single instruction. The program memory utilization and computational speed is optimized. Fuzzy Logic dedicated structures in ST52T410/ ST52x420 ICU' s can be ex ploi ted t o model complex systems with high accuracy in a useful and easy way. F uz z y E x pe r t S y s t em s f o r o ve r a ll s y s t e m management and fuzzy Real time Controls can be designed to increase performances at highly competitive costs. The linguistic approach characterizing Fuzzy Logic is based on a set of IF-THEN rules, which describe the control behavior, as well as on Membership Funct ions, which are associat ed to input and output variables. Up to 334 Membership Functions, with triangular and trapezoidal shapes, or singleton values are available to describe fuzzy variables. T h e T i m e r / P W M p e r i p h e r a l a l l o w s t h e management of power devices and timing signals, implementing different operating modes and high frequency PWM (Pulse With Modulation) controls. Input Capture and Output Compare functions are available on the TIMER. The programmable Timer has a 16 bit Internal Prescaler and an 8 bit Counter. It can use internal or external Start/Stop signals and clock. An internal programmable Watchdog is available to avoid loop errors and to reset the ICU.
ST52T410/T420/E420
ST52x420 includes an 8-bit Analog t o Digit al Converter with an 8-analog channel Multiplexer. Single/Multiple channels and Single/Sequence conversion modes are supported. I n order to optimize energy consumption, two different power saving modes are available: Wait mode and Halt mode. Program Memory (EPRO M/O TP) addressing capability addresses up to 8 Kbytes of memory locations to store both program instructions and permanent data. EPROM can be locked by the user to prevent external undesired operations. Operations may be performed on data stored in RAM, allowing the direct combination of new input and feedback data. All bytes of RAM are used like Register File. OTP (One Time Programmable) version devices are fully compatible with the EPROM windowed version, which may be used for prototyping and pre-production phases of development. A powerful development environment consisting of a board a nd sof t ware t oo ls allow s an eas y configuration and use of ST52T410/ST52x420. T h e VI S U AL FI V ET M lo ws al o ol ts of t wa r e development of projects through a user-friendly graphical interface and optimization of generated code.
1.2 Functional Description ST5 2T410/ ST52x420 I CUs can work in t wo modes: nMemory Programming Mode nWorking Mode according to RESET and Vpp signals levels (see pins description). Note: useWhen RESET=0 it is advisable not to the sequence ª101010ª to port PA (7 : 2).
1.2.1 Memory Programming Mode. The ST52T410/ST52x420 memory is loaded in the Memory Programming P has e. All f uzzy and st andard instr uc t ions are writ t en inside t he memory. This phase starts by setting the control signals as illustrated below:
RESET Vss
TEST
Vss
VPP 12V/VDD
7/84
ST52T410/T420/E420
When this phase starts, the ST52T410/ST52x420 core are set to RESET status; then 12V are applied t o t h e V p p p i n i n o r d e r t o s t a r t E P R O M programming. A signal applied to PB1 is used to increm ent t he memory address; t he dat a i s supplied to PORT A (see EPROM programming for further details).
1.2.2 Working mode. Below are the control signals of this mode:
RESET
VDD
TEST VSS
VPP VSS
The processor starts the working phase following the inst ructions, which have been previously loaded in the memory. ST52T410/ST52x420's internal structure includes a computational block, CONTROL UNIT (CU) / DATA PROCESSING UNIT (DPU), which allows
Figure 1.1 ST52x420 SO28 Pin Configuration
8/84
RESET
OSCOUT OSCIN TEST INT/PC0 T0OUT/PC1 T1OUT/PC2 T2OUT/PC3 Ain0/PB0 Ain1/PB1 Ain2/PB2 Ain3/PB3 VDDA GNDA
1
2 3 4 5 6 7 8 9 10 11 12 13 14
p roc es sing of bo ol ean f un ct io ns and f u zzy algorithms. The CU/ DPU can manage up to 334 different M e mbe r shi p F un ct io ns f or t h e f u zz y rul es antecedent part. The rule consequents are ªcrispº values (real numbers). The maximum number of r ules t ha t ca n be de f in ed i s lim it ed by t h e d i m e n s i o ns o f t h e i m p le me n t e d s t an da r d algorithm. EP RO M is t h en share d bet wee n f uzzy and standard algorithms. The Membership Function dat a is st ored inside t he f i rst 1024 memory locations. The Fuzzy rules are parts of the program instructions. The Control Unit (CU) reads the information and the status deriving from the peripherals. Arithmetic calculus can be performed on these values by using the internal CU and the 128 bytes of RAM, which supports all computations. The peripheral input can be fuzzy and/or arithmetic output, or the values contained in Data RAM and EPROM locations.
SO28
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VDD VSS VPP PA0/T0RES PA1/T0OUT PA2/T1OUT PA3/T2OUT
PA4/T0STRT PA5/T0CLK PA6
PA7/PB7/Ain7
PB6/Ain6 PB5/Ain5 PB4/Ain4
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