Leakage Tutorial

A Bit-Serial Approximate Min-Sum LDPC Decoder and FPGA Implementation Ahmad Darabiha, Anthony Chan Carusone, Frank R . Ksc hischangUniversity of Toronto, Toronto, CanadaISCAS, Kos, GreeceMay 2006 IS CAS 2006Outline• Introduction to LDPC co des/decoders• Proposed techniques• B it-se rial message passing• Approximate Min-S um decoding• FPGA implementation• Conclusion2IS CAS 2006Introduction• Low -Density Parity-C heck (LDPC) codes• A sub-class of Error Control Codes (ECC)• Perform better than Turbo and Reed-Solomon codes• Approach Shannon limit • LDPC codes are adopted for • IEEE 802.3 10Gbit Ethernet standard-3• Input B ER > 10-13• Output B ER < 10 • Code rate 0.84 • DVB -S2 Digital Video B roadcast standard3IS CAS 2006LDPC Codes: StructureM=5 checkD = 4 nodesCN=1 0D = 2V variablenodes1 0 0 10 10 0 100 11 0 10 0 10 00 0 0 10 110 10H = MxN1 10 0 0 0 10 0 10 0 1 0 10 0 10 1• Each bit participates in D parity checksv• Each check consists of D bitsc• Good LDPC codes are long (large N) and with a random-like graph4IS CAS 2006Min-Sum LDPC Decoding • A form of iterative message passing decodingchecks• Messages in Log-Likelihood Ratio (LLR) Log(P(x=0) / P (x=1))•CV m• Each iteration does two updates: 1V V2 m-1• Check node updatec = chk(v , .., v )m 1 m-1variable = (sgn(v) .. sgn(v )) Min(|v |, …, |v |)1 m-1 1 m-1checksC• Variable node update n-1C2C1 Vnv = var(c , c ,..,c ) n 1 2 n-1 = ...