VLSI Lab Tutorial 3

VLSI Lab Tutorial 3 Virtuoso Layout Editing Introduction 1.0 Introduction The purpose of this lab tutori al is to guide you through the design process in creating a custom IC layout for your CMOS inverter de sign. The layout repres ents masks used in wafer fabs to fabricate a die on a silicon wafer, which then eventually are packaged to become integrated circuit chips. Upon completion of this tutori al, you should be able to: - Create a mask layout of the CMOS inve rter that you have designed earlier. - Check that your layout satisfies the design rules of a 0.18 micron process technology using DRC. - Extract a netlist including parasitic resi stances and capacitances from the layout. - Check that your layout passes the automa tic verification against the inverter schematic created earlier. . ! More information can be found in thline edocum on entation under the Custom IC and Deep Submicron Design category. U nder Custom IC Layout, there is the Layout section that you may find helpful. 2.0 Inverter Layout Overview The pictures on the facing page present an i nverter layout very similar to the one you are about to create. The only si gnificant difference should be the transistor widths. The inverter you create should have transistor widthms atching the values you determined in the tutorial 1. This layout is in the style of standar d usceedll sfor automated placement and routing of random logic. This does not, however, mean that ...