VLSI Design-ASPDAC tutorial pages

Tutorial Three Trends and Challenges in VLSI Technology Scaling Towards 100nm Stefan Rusu (Coordinating Presenter) Intel Corporation, USA stefan.rusu@intel.com Manoj Sachdev University of Waterloo, Canada msachdev@ece.uwaterloo.ca Christer Svensson Linkoping University, Sweden chs@isy.liu.se Bram Nauta University of Twente, The Netherlands B.Nauta@el.utwente.nl Abstract Moore's Law drives VLSI technology to continuous increases in transistor densities and higher clock frequencies. This tutorial will review the trends in VLSI technology scaling in the last few years and discuss the challenges facing process and circuit engineers in the 100nm generation and beyond. The first focus area is the process technology, including transistor scaling trends and research activities for the 100nm technology node and beyond. The transistor leakage and interconnect RC delays will continue to increase. The tutorial will review new circuit design techniques for emerging process technologies, including dual Vt transistors and silicon-on-insulator. It will also cover circuit and layout techniques to reduce clock distribution skew and jitter, model and reduce transistor leakage and improve the electrical performance of flip-chip packages. Another focus area is the circuit design and the techniques used to minimize capacitive and inductive noise. The tutorial will review models of electrical interconnects, including inductance and skin effect. These models ...