Synopsys Design Compiler Tutorial

King Fahd University of Petroleum and MineralsComputer Engineering DepartmentCOE 561Digital Systems Design and Synthesis(Course Activity)Synthesis using Synopsys Design Compiler TutorialThe Synthesis Flow (What, How & Why?)Presented byMohammad IbrahimAl-BehwashiAdvisorDr. Aiman El-MalehDate 16-11-2006Fall Semester (061)Agenda• Introduction to Design Compiler• The Synthesis Process Flow• Explain Each Step in the Flow• Apply an example of a combinational circuit under Design Analyzer• Apply an example of a sequential circuit • Show the commands of each step21Introduction• The Design Compiler is the core of the Synopsys synthesis software products. It includes tools that synthesis the HDL designs into optimized technology-dependent, gate level designs. It can optimize for speed, area and power. 3Basic Synthesis Flow D E S I G N C O M P I L ER Mapped, technology VHDL or Verilog File dependent netlist Synthesis; Optimize (go for place for area, speed and and route / post power layout synthesis) A view of the Design Compiler Function42Synthesis, Optimization and Compilation• Synthesis: is the process that generates a gate-level netlist for an IC design that has been defined using a Hardware Description Language (HDL). Synthesis includes reading the HDL source code an optimizing the design from that description.• Optimization: is the step in the synthesis process that attempts to implement a combination of library cells ...