natarajan embedded tutorial FINAL

Technological Innovations to Advance Scalability and Interconnects in Bulk and SOI Sreedhar Natarajan and Andrew Marshall Texas Instruments Incorporated, 1350 N.Central Expressway, MS 3737, Dallas, TX Email: sn@ieee.org Introduction requirements of SOI, and the ability to better position With technology scaling rapidly, there is increased need critical path components in SOI. for improved performance. While improved performance can be achieved with lower threshold voltages, leakage Transistor Doping Profiles will be a major issue at technologies below 0.1µm. The sources and drains of SOI devices have shallow Interconnect scaling is not expected to keep up with junction depths compared to junctions in bulk material. component scaling, resulting in higher capacitance losses The use of SOI results in a well-defined source/drain, and challenges in signal routing. We consider how scaling which is relatively easy to maintain with technology will impact design for low power and high performance scaling. This is not the case with bulk material, where applications. SOI may be a solution for some issues like junction scaling becomes more difficult as geometries SER due to the presence of buried oxide. Performance can reduce. Reduction in volume of the SOI source/drain be enhanced by SOI technology due to the absence of does, however, tend to lead to higher resistance transistors junction capacitance (figure 1). The combination of short than their bulk ...