Strained and unstrained silicon nanowire-array MOSFETs [Elektronische Ressource] : fabrication and physical analysis / Stefan Habicht

Strained and Unstrained SiliconNanowire-Array MOSFETs:Fabrication and Physical AnalysisVon der Fakult at fur Mathematik, Informatik und Naturwissenschaftender RWTH Aachen University zur Erlangung des akademischen Gradeseines Doktors der Naturwissenschaften genehmigte Dissertationvorgelegt vonDiplom-Ingenieur Stefan Habichtaus FriedrichrodaBerichter: Universiatst professor Dr. S. MantlUniversit atsprofessor Dr. D. Grutzmac herTag der mundlic hen Prufu ng: 21. Juli 2011Diese Dissertation ist auf den Internetseiten der Hochschulbibliothek online verfugb ar.AbstractOver the past ve decades geometric scaling of transistor dimensions has beenthe driving element to improve device performance and simultaneously decreasethe cost per function. Today, state of the art MOSFETs feature e ective gatelengths of only a few tens of nanometers pushing the conventional MOSFETelectronics towards nanoelectronics. The International Technology Roadmap forSemiconductors (ITRS) predicts the 18 nm node for the year 2018, that requiresa physical gate length of 7 nm or less. It has been widely accepted that the pathfor the next decades is going to be far more demanding. This includes the intro-duction of new device concepts (e.g. nanowire or FinFETs), complex materialengineering (e.g. III-V, strain engineering) and handling the variability of de-vices (e.g. random dopant uctuation, line-edge roughness) as channels approachatomic scales.