Impulse Tutorial: Complex FIR PowerPC ML507 EDK10.1

Tutorial: Creating a Complex FIR Filter on a Virtex-5 FX Platform (EDK 10.1) 1
1 Tutorial: Creating a Complex FIR Filter on a Virtex-5 FX
Platform (EDK 10.1)
Overview
This detailed tutorial will demonstrate how to use Impulse C to create, compile and optimize a digital
signal processing (DSP) example for the PowerPC platform. We will also show how to make use of
the Auxiliary Processor Unit (APU) and Fabric Co-processor Bus (FCB) provided in the PowerPC
platform.
The goal of this application will be to compile the algorithm (a Complex FIR Filter function) as
hardware on the FPGA. The PowerPC will be used to run test code (producer and consumer
processes) that will pass text data into the algorithm and accept the results.
This example makes use of the Xilinx ML507 Evaluation Platform. The board features a Virtex-5
FXT FPGA with a PowerPC 440 embedded processor core. This tutorial also assumes you are using
the Xilinx EDK 10.1i (or later) development tools.
This tutorial will require approximately one hour to complete, including software run times.
Note: this tutorial is based on a sample DSP application developed by Bruce Karsten of Xilinx, Inc. A
more complete description of the algorithm can be found in the Impulse C User Guide, in the Getting
Started Tutorial #2. This tutorial assumes that you have are familiar with the basic steps involved in
using the Xilinx EDK tools. For brevity this tutorial will omit some EDK details that are covered in
introductory EDK and ...