Gate-level current modeling of digital integrated circuits for conducted chip emission characterization [Elektronische Ressource] = Modellierung der Stromaufnahme digitaler integrierter Schaltungen auf Gatterebene zur Charakterisierung der leitungsgebundenen Chip-Emission / vorgelegt von Andreas Gstöttner

Gate-Level Current Modeling ofDigital Integrated Circuits forConducted Chip EmissionCharacterizationModellierung der Stromaufnahme digitalerintegrierter Schaltungen auf Gatterebene zurCharakterisierung der leitungsgebundenenChip-EmissionDer Technischen Fakultat der Universitat Erlangen-Nurnberg zur Erlangung des GradesDOKTOR-INGENIEURvorgelegt vonAndreas GSTOTTNERErlangen - 2010Als Dissertation genehmigt vonder Technischen Fakultat derUniversitat Erlangen-Nurnberg Tag der Einreichung : 01. Februar 2010Tag der Promotion : 11. Marz 2010Dekan : Prof. Dr.-Ing. Reinhard GermanBerichterstatter : Prof. Dr.techn Mario HuemerProf. Dr.-Ing. Klaus HelmreichAcknowledgementThis work would not have been accomplished in that way without the help andsupport of several people to whom I want to express my sincere gratitude. First ofall, I wish to thank Prof. Dr. Mario Huemer for being my research advisor and hisguidance and support.Special thanks to Thomas Steinecke for consistently supporting me during allstages of this work, his organizational e orts, and the precious ideas and inspiringdiscussions. I am also very thankful to all colleagues at In neon Technologies whocontributed to this work, particularly Jack Kruppa and Mehmet Goekcen. Theirfull support and many interesting discussions turned out to be indispensable forthe success of this thesis.I would like to thank Prof. Dr.