Fully programmable LDPC decoder hardware architectures [Elektronische Ressource] / von Christiane Maja Beuschel

Fully Programmable LDPC DecoderHardware ArchitecturesDISSERTATIONzur Erlangung des akademischen Grades einesDOKTOR–INGENIEURS(DR.–ING.)der Fakult¨at fu¨r Ingenieurwissenschaftenund Informatik der Universit¨at UlmvonCHRISTIANE MAJA BEUSCHEL¨AUS WANGEN IM ALLGAUGutachter: Prof. Dr.-Ing. Hans-J¨org PfleidererProf. Dr.-Ing. Norbert WehnAmtierender Dekan: Prof. Dr.-Ing. Michael WeberUlm, 22.04.2010Fully Programmable LDPC DecoderHardware ArchitecturesAbstractIn recent years, the amount of digital data which is stored and transmitted for privateand public usage has increased considerably. To allow a save transmission and storage ofdata despite of error-prone transmission media, error correcting codes are used. A largevariety of codes has been developed, and in the past decade low-density parity-check(LDPC) codes which have an excellent error correction performance became more andmore popular. Today, low-density parity-check codes have been adopted for several stan-dards, and efficient decoder hardware architectures are known for the chosen structuredcodes. However, the existing decoder designs lack flexibility as only few structured codescan be decoded with one decoder chip. In consequence, different codes require a redesignof the decoder, and few solutions exist for decoding of codes which are not quasi-cyclic orwhich are unstructured.