Efficient protocol design flow for embedded systems [Elektronische Ressource] / vorgelegt von Daniel Dietterle

Efficient Protocol Design Flow for Embedded SystemsVon der Fakult¨at fu¨r Mathematik, Naturwissenschaften und Informatikder Brandenburgischen Technischen Universit¨at Cottbuszur Erlangung des akademischen GradesDoktor der Ingenieurwissenschaften(Dr.-Ing.)genehmigte Dissertationvorgelegt vonDipl.-Inf.Daniel Dietterlegeboren am 10. Februar 1978 in Eberswalde-FinowGutachter: Prof. Dr.-Ing. Rolf KraemerGutachter: Prof. Dr.-Ing. Jorg¨ NolteGutachter: Prof. Dr.-Ing. Adam WoliszTag der mu¨ndlichen Pru¨fung: 25. Februar 2009iiAbstractIt is predicted that, in the next years, wireless sensor networks could be massivelydeployed in a wide variety of application areas, such as agriculture, logistics, au-tomation, or infrastructure monitoring. An extremely low power consumption,high dependability, and low cost are common requirements for sensor nodes in allthese applications. This can be achieved only by tiny, power-efficient microcon-trollers and communication systems integrated on a single chip.Formaldescriptiontechniques,suchasSDL(SpecificationandDescriptionLan-guage), are suitable to formally prove properties of models designed in these lan-guages. Code generators facilitate the automatic transformation of SDL modelsinto software implementations, while preserving the properties of the model and,thus, achieving high system dependability.