Dynamic coarse grained reconfigurable architectures [Elektronische Ressource] / presented by Basher Shehan

Dynamic Coarse Grained ReconfigurableArchitecturesDISSERTATIONFOR THE DEGREE OF DOCTOR OF ENGINEERING (DR.-ING.)SUBMITTED TO THE DEPARTMENT OF COMPUTER SCIENCE OF THE UNIVERSITY OFAUGSBURGPRESENTED BYBASHER SHEHANIN 201021. Reviewer: Prof. Dr. Theo Ungerer2. Reviewer: Prof. Dr.-Ing. Rudi KnorrDay of the defense: 23.11.2010Signature from head of PhD committee:AbstractCoarse grained reconfigurable processors have gained more popularity in the last years,as they introduce a new way for a dynamic and programmable execution similar toFPGA and tend to achieve the performance of application specific hardware. The re-configurability on instruction level grants these architectures a big dynamicity and abil-ity to embrace the diversity of the applications. Nevertheless, managing the hardwareresources in the software prevents from undertaking many dynamical reactions neededby the reconfiguration task at runtime to be adaptive to the dynamic program execution.However, an adaptive architecture can face the diversity of applications dynamically inthe hardware without any software manipulation. On the other hand, the need for moreflexibility to manage the underlying hardware structures increases the demands on theconfiguration hardware unit.This work focuses on the design and optimization of reconfigurable coarse grainedprocessors. In addition, it concerns with the implementation of the configuration taskin the hardware.