Architecture synthesis for adaptive multiprocessor systems on chip [Elektronische Ressource] / von Harold Ishebabi

DepartmentforComputerScienceProfessorshipforEngineeringArchitectureSynthesisforAdaptiveMultiprocessorSystemsonChipDissertationzurErlangungdesakademischenGrades“doctorrerumnaturalium”(Dr.rer.nat.)inderWissenschaftsdisziplin“TechnischeInformatik”eingereichtanderMathematisch-NaturwissenschaftlichenFakultat¨derUniversitat¨ PotsdamVonHaroldIshebabiPotsdam,den29.05.20091.Berichterstatter:Prof.Dr.rer.nat.ChristopheBobda2.Prof.PaulChow3.Prof.Dr.AachimRettbergThis work is licensed under a Creative Commons License: Attribution - Noncommercial - Share Alike 3.0 Unported To view a copy of this license visit http://creativecommons.org/licenses/by-nc-sa/3.0/ Published online at the Institutional Repository of the University of Potsdam: URL http://opus.kobv.de/ubp/volltexte/2010/4131/ URN urn:nbn:de:kobv:517-opus-41316 http://nbn-resolving.org/urn:nbn:de:kobv:517-opus-41316 Hiermit erklare¨ ich,dass dieArbeit ankeiner anderenHochschule eingereichtsowie selbstandig¨ undnurmitdenangegebenenMittelnangefertigtwurde.Potsdam,29.05.2009(HaroldIshebabi)AbstractThis thesis presents methods for automated synthesis of flexible chip multiprocessor systems fromparallelprogramstargetedatFPGAstoexploitbothtask-levelparallelismandarchitecturecustomiza-tion. Automated synthesis is necessitated by the complexity of the design space.