Text Regarding Comment #91

85.8.4.2 Receiver interference tolerance test at TP3 The receiver interference tolerance tests shall be implemented using the receiver interference tolerance parameters summarized in Table 85–7. The tests are to be applied to each 40GBASE-CR4 or 100GBASE-CR10 lane. Parameter Test 1 Test 2 Units Value Value -12 -12 Target BER 10 10 Minimum fitted insertion loss coefficients a =2.15 A =6.04 dB /root-GHz1 1 a =0.78 a =0.94 dB /GHz2 22 a =0.03 a =0.08 dB /GHz4 4a Applied SJ (min. peak-to-peak) '0.115 '0.115 UI bApplied RJ (min. peak-to-peak) '0.130 '0.130 UI Applied DCD (min. peak-to-peak) '0.035 '0.035 UI Calibrated far-end crosstalk (min. RMS) '6.0 '2.2 mV Calibrated ICN (min. RMS) – MDNEXT '3.7 '3.7 mV a Applied SJ frequency >15 MHz , specified at TP0 b Applied random jitter at TP0 is specified at 10–12 85.8.4.3 Test setup The interference tolerance test is performed with the setup shown in Figure 85.X Transmitter Control MDI Test channel LUTPattern n pair ReceiverCable Tx/RxGeneratorTwinaxial cable Under assembly PCBn=4,10,… Testtest fixture 3 or 9 Tx Test reference Editors note: [Add Tx under receiver under test with dashed line in receiver under test block and pattern generator connection label] Figure 85.X interference tolerance test setup 85.8.4.4 Test channel The test channel consists of: 1. A cable assembly 2. A cable assembly test fixture 3. A connecting path from the pattern ...