tutorial-memory-final

mmInstr DataCache CacheITLB DTLBRegFileTutorial Outline 8:30 8:45Introduction and motivation 8:45 9:05Sources of power in CMOS designs 9:05 9:30Power analysis tools and techniques 9:30 10:30Gate & functional unit design issues & techniques10:30 10:50 BREAK10:50 12:15 Architectural level issues and techniques12:15 1:30 LUNCH 1:30 2:30Low power memory system design 2:30 3:30Software level issues and techniques 3:30 3:50BREAK 3:50 4:30Software level issues and techniques, con’t 4:30 - 4:45 Future challengesISCA Tutorial: Low Power Design Memories.1 ©MJI&VN, PSU, 2000Typical Memory HierarchyOn Chip ComponentsControleDRAMSecondarySecondMain StorageLevelMemory (Disk)Datapath Cache(DRAM)(SRAM)DEC 21164a (2.0V , 0.35 , 400MHz, 30W max)dd–caches dissipate 25% of the total chip powerDEC SA 110 (2.0V, 0.35 , 233MHz, 1W typ) – no L2 on-chipdd–I$ (D$) dissipate 27% (16%) of the total chip powerISCA Tutorial: Low Power Design Memories.2 ©MJI&VN, PSU, 20001lllImportance of OptimizingMemory System EnergyMany emerging applications are data intensiveFor ASICs and embedded systems,memory system can contribute up to 90%energyMultiple memories in future System on chip designsISCA Tutorial: Low Power Design Memories.3 ©MJI&VN, PSU, 20002D Memory Architecturek j bit line2word lineAjAj+1 storage(RAM) cellAk 1jm2Sense Amplifiers amplifies bit line swignRead/Write CircuitsA0 selects ...