tutorial-clock

Power Reduction Techniques in the SoCClock NetworkLow Power Design for SoCs ASIC Tutorial SoC Clock.1 ©M.J. Irwin, PSU, 1999Clock Powerl Why clock power is important/large» Generally the signal with the highest frequency» Typically drives a large load– all sequential logic elements– all precharged/dynamic logic– distributed throughout chip, so lots of wiring» DEC 21164’s clock accounts for 40% of total chip power– 3.75nF total clock load– 20W (out of 50W) in clock distribution networkLow Power Design for SoCs ASIC Tutorial SoC Clock.2 ©M.J. Irwin, PSU, 19991Processor Power BudgetsClockDatapathMemoryI/O (pads)Inner circle: low end embedded microprocessorNext circle: high end CPU with on-chip cacheNext circle: MPEG2 decoder ASICOuter circle: ATM switch ASICLow Power Design for SoCs ASIC Tutorial SoC Clock.3 ©M.J. Irwin, PSU, 1999Clock Power Reduction2P = CV fclock ddl Minimize voltage (V) using half swing clocksl Minimize clock load (C)» clock gating» careful routing, distributed driversl Minimize clock frequency (f)» DET flipflops» localized PLL to multiply frequency of clockl GALS design approachLow Power Design for SoCs ASIC Tutorial SoC Clock.4 ©M.J. Irwin, PSU, 19992Reduced Swing ClockVdd N-device clockP-device clockGndRegular ClockVddP-device clockVtpVtn N-GndHalf Swing ClockLow Power Design for SoCs ASIC Tutorial SoC Clock.5 ©M.J. Irwin, PSU, 1999Half Swing Clocksl Advantages» as long as Vtn (Vtp) less (greater) ...