Tutorial 1.fm

Xilinx-Lava User Guide1 Describing Netlists1.1 Implementing Combinational Logic in LUTsStructural netlists are described in Lava by composing functions that represent basic library elements or composite circuits. This is very similar to the way the structura netlists are described in VHDL or in Verilog which rely on netlist naming to compose circuit elements. Later we present combinators which provide a much more powerful-way to combine circuits.Most hardware description languages provide a library of basic gates that correspond to the Xilinx Unified Library components. Designers can build up netlists by creating instances of these abstract gates and writing them together. The implementation soft-ware maps these gates to specific resources on the FPGA. Most logic functionality is mapped into the slices of CLBs. The top half of a Virtex-II slice is shown in Figure 1.1 on page 2.Lava provides a more direct way to specify the mapping into CLB, slices and LUTs. Just like the Xilinx Unified Library the Xilinx Lava library contains specific functions (circuits) that correspond to resources in a Virtex slice e.g. muxcy and xorcy. However, instead of trying to enumerate every possible one, two, three and four input function that can be realized in a LUT Lava instead provides a higher order function for creating a LUT configuration from a higher level specification of the requited function.As an example consider the task of configuring a LUT to be a two input ...