Logic and verification simulation Tutorial

Cadence VHDL/Veril og Simulation Guide and Tu torialfor use at the University of CincinnatiWei YangJanuary 2 003(Updated Jan 04, H . Carter)This guide describes, via a tutorial, how to set up the personal environment (paths andevnrionment variables), and simulate VH D L (or Verilog) models using the Cadencetools. The tutorial describes VH D L simulation, but Verilog simulation should beidentical except that the model files traditionally end in .v rather than .vhd or .vh dl. TheCadence simulator can simulate either or both VH D L and Verilog models.The Cadence tools were initially acquired in 2 001 and have been gaining increasing useas educators and researchers in the Electrical and Computer Engineering and ComputerScience (ECE CS) department have become familiar with them. All of the Cadence toolsand documentation are located in /opt/CAD/Cadence/ and can be executed only fromSun workstations served by the department servers. Since these tools are commerciallylicensed, please do not point any UR L 's to them from public websites.This guide is presented in three sections:1 .H ow to set up your environment to view the documents and run the simulator tools.You can skip this section if your environment is already set up to access the Cadencetools.2 .Executing the VH D L /Verilog simulator. Two approaches can be used to simulateVH D L /Verilog models: 1 ) manually executing a series of three programs to compile,elaborate, and simulate the ...