ICCAD-Tutorial

System Level Design and Verification Using aSynchronous LanguageGer´ ard Berry Michael Kishinevsky Satnam SinghEsterel Technologies Intel Corp. XilinxFrance Hillsboro, OR San Jose, CAgerard.berry@esterel- michael.kishinevsky@intel.com satnam.singh@xilinx.comtechnologies.comABSTRACT Hierarchical description of control is not possible in Verilogor VHDL. As a result, minor modi cations in the speci -Synchronous languages such as Esterel, Lustre, Signal, andcation can lead to major changes in the design. For ex-others were originally developed for safety-critical embed-ample, waiting for three concurrent signals that can arriveded software and compiled into C. They have recently beenin any order instead of two requires ve more states andextended to hardware with new language features and com-fourteen more transitions. This makes debugging di cult,pilers to RTL. Contrary to traditional HDL languages (Ver-limits model reuse, and leads to hidden communication bugsilog, VHDL) and recent system-level languages (SystemC,that might be detected very late in the design ow, or evenSystem Verilog), they have well de ned formal semantics,remain undetected. Traditional control-dominated designwhich facilitate bug avoidance using correct-by-constructionproductivity is relatively low.compilation and veri cation techniques.Recently there have been signi cant development in theThe tutorial will demonstrate what the synchronous lan-area of system-level languages ...