HPCA-2011-Tutorial

PROGRAMMING FPGA ACCELERATORS USING ROCCCHPCA 2011 TUTORIAL FEBRUARY 12-16, 2011, SAN ANTONIO, TXJason Villarreal ABSTRACTJacquard Computing Inc. ROCCC (Riverside Optimizing Compiler for Configurable 588 Technology Court Computing) is a C to VHDL compilation framework specifically Riverside, CA 92507 USA focused on FPGA-based code acceleration. Unlike similar jason@jacquardcomputing.com tools designed for high-level synthesis, ROCCC does not support the generation of arbitrary hardware circuits. Rather, its focus is on compile time transformations and optimizations Walid Najjaraimed at generating an efficient circuit from a loop nest. Its Computer Science & Engineeringobjectives are to maximize parallelism within the constraints of University of California Riversidethe target device, optimize clock cycle time by efficient Riverside, CA 92521 USApipelining and minimize the area utilized. Furthermore, najjar@cs.ucr.eduROCCC relies on extensive and unique loop analysis techniques to increase the reuse of data fetched from off-chip memory. ROCCC 2.0 is a free and open source tool that supports a modular bottom-up approach to the programming of FPGA accelerators, supporting code reuse at multiple levels while maintaining full compatibility with C. It has been ported to several platforms for both embedded and high-performance applications. These include the Xilinx development boards, the Pico Computing platforms and the Convey Computers HC-1.LECTURE ...