encoding-tutorial-talk

Memory Bus Encoding forLow Power: A TutorialWei-Chung Cheng and Massoud PedramUniversity of Southern CaliforniaDepartment of EE-SystemsLos Angeles CA 90089Outline• Background Memory Bus Encoding Techniques– Algebraic codes– Permutation codes– Probabilistic codes ConclusionsISQED 2001Memory Bus Encoding For Low Power 1Power Dissipation Equation2• P~VCfNLow Power Techniques Memory Modules– Voltage Scaling –Fixed– Capacitance Reduction – High– Frequency Scaling– High– Switching Activity– Memory BusReductionEncodingISQED 2001Bus Encoding ExampleBinary Code Gray CodeA1: 0000 B1: 00000001A2: 0001B2:A3: 0010 0011B3:A4: 0011 0010B4:SA=6 SA=4ISQED 2001Memory Bus Encoding For Low Power 2Generic Bus EncodingArchitectureAddressEncoder DecoderCPU: Data Memory:Code WordciSource Word Source Words siiISQED 2001Bus Encoding TaxonomyRedundancy Irredundant: Gray, PyramidRedundant: T0, Bus Invert, Working ZoneCircuit Non-terminated TTL, LVCMOSTerminated RAMBUS, GTLSignal Level Level Sign SignalingalingTTrranansitiositionn S SiigngnalalininggLocation On-chip Bus Between CPU core and CachesHost Bus Between Pentium and ChipsetMemory Bus Between Chipset and DRAMAddress/Data SeparatedMultiplexMultiplexeeddMultiplexing Non-multiplexed SRAMMultiplexed DRAMISQED 2001Memory Bus Encoding For Low Power 3Code Classification1. Algebraic Codesc op x : op is a binary operationi2. Permutation Codesf(c): fis a fixed functioni3. ...