Benchmark Results for High-Speed 4-bit Accumulators Implemented in Indium Phosphide DHBT Technology

International Journal of High Speed Electronics and SystemsVol. 14, No. 3 (2004) 646{651°c World Scientiflc Publishing CompanyBENCHMARK RESULTS FOR HIGH-SPEED 4-BITACCUMULATORS IMPLEMENTED IN INDIUM PHOSPHIDEDHBT TECHNOLOGYSTEVEN EUGENE TURNER and DAVID E. KOTECKIDepartment of Electrical & Computer EngineeringUniversity of Maine, Orono, ME 04469-5708, USAHigh-speed accumulators are frequently used as a benchmark of the high-speed perfor-mance and ability to yield large scale circuits in InP double hetereojunction bipolar(DHBT) processes. In previous work, we reported test results of an InP DHBT 4-bitaccumulator with 624 transistors operating at 41 GHz clock frequency with a powerconsumption of 4.1W. In this work, we report on modiflcations that allow the circuit tooperate at a lower supply voltage and a corresponding lower power consumption. Simu-lationresultsforthismodiflcationindicatethata16%powerreductioncanbeobtained,while maintaining a high-speed operating frequency of 40 GHz.1. IntroductionHigh-speedaccumulatorcircuitsareacriticalcomponentofdirectdigitalsynthesiz-ers (DDS), which are useful for generating frequency-agile waveforms with complexmodulation. To allow direct generation of these waveforms at radio frequencies upto X-band, the accumulator circuit must operate at clock rates=30 GHz. The ac-cumulator must also have a wide bit width in order to provide adequate frequencyresolution, thus requiring transistor counts approaching 5000 devices ...