070810 Characterization of EEMBC Benchmark Suite

ƒƒƒƒƒƒƒƒƒƒƒ An Industry Standard Benchmark Consortium Characterization of the EEMBC Benchmark Suite By Jason Poovey, North Carolina State University EEMBC addresses the needs of embedded designers by providing a diverse suite of processor benchmarks organized into categories that span numerous real-world applications. Research done at North Carolina State University investigates the benchmark suites through the use of benchmark characterization to create a description of each workload. Benchmark characterization involves re-describing a workload as a set of quantifiable abstract attributes. Designers can then use these measured attributes to determine program similarity. By combining these characteristics with their knowledge of the actual application, designers can select the most relevant benchmarks from the EEMBC suite to test the potential in situ performance of an embedded processor. We used a mixture of design characteristics including instructions/clock (IPC), branch mis-prediction ratios, and dynamic instruction percentages. We also collected hardware design metrics for caches and functional units that target the hardware requirements to achieve certain performance goals. Methodology This study collected characteristics for the MIPS, PowerPC, x86, and PISA (used in Simplescalar) architectures. The resulting combination of metrics provides an accurate representation of the workload’s activity. Thus, designers ...