Verification of Data Flow Graphs using Temporal Logic

• mémoire
• exposé
• mémoire - matière potentielle : place

Formal VLSI Correctness Verification, VLSI Design Methods-II, ed. L.J.M. Claesen, North-Holland, 1990, pp. 169-178 Verification of Data Flow Graphs using Temporal Logic Gjalt G. de Jong * Department of Electrical Engineering, EH 7.26 Eindhoven University of Technology P.O. Box 513, 5600 MB Eindhoven, The Netherlands Tel. +31-40-473345, E-mail: .

• model checking
• merge nodes
• outgoing edge
• linear time
• data flow graph
• nodes
• node
• state
• time