WCIT2011_HDL models simulation

• exposé - matière potentielle : the simulation flow
• cours - matière potentielle : assignments

Available online at Procedia Computer Science 00 (2009) 000–000 Procedia Computer Science 2nd World Conference on Information Technology HDL model simulation-based verification in a VHDLVisualizer visualization environment Dominik Macko*, Katarína Jelemenská, Pavel Čičák Slovak University of Technology, Faculty of Informatics and Information Technologies, Ilkovičova 3, 84216 Bratislava 4, Slovakia Abstract Throughout the world, many VHDL (Very-high-speed integrated circuit Hardware Description Language) simulators exist, but only a few of them support the visualization of VHDL model simulation.

• hdl
• vhdl visualizer
• signal value
• visualization environment
• vhdl model visualization
• port connector color
• representation
• simulation
• bit
• design