RTL Synthesis

• exposé
• expression écrite

1BR 6/01 1 RTL Synthesis • RTL = Register Transfer Level • RTL code (Verilog, VHDL, or something else) completely specifies – all registers – Logic operations – Arithmetic operation • Synthesis will convert these to meet some combination of an area + delay constraint – Boolean minimization techniques used to improve both area and speed – Different area, speed constraints will produce different gate level netlists, but will be functionally equivalent BR 6/01 2 Random Logic vs Arithmetic RTL • General boolean minimization techniques work well for random logic to meet area/speed constraints • Not true for Arithmetic operations (addition, multiplication, etc) –

• synopsys
• ripple
• cell functionality
• synopsys synthesis
• tutorial file
• delay
• adder
• carry
• architecture
• library