October This is preliminary information on a new product now in development orundergoing evaluation Details are subject to change without notice

Rev. 1.6 October 2002 1/156 This is preliminary information on a new product now in development orundergoing evaluation. Details are subject to change without notice. ST72324J/K 8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, 4 TIMERS, SPI, SCI INTERFACE PRELIMINARY DATA n Memories – 8 to 32K dual voltage High Density Flash (HD- Flash) or ROM with read-out protection capa- bility. In-Application Programming and In- Circuit Programming for HDFlash devices – 384 to 1K bytes RAM – HDFlash endurance: 100 cycles, data reten- tion: 20 years at 55°C n Clock, Reset And Supply Management – Enhanced low voltage supervisor (LVD) for main supply with 3 programmable reset thresholds and auxiliary voltage detector(AVD) with interrupt capability – Clock sources: crystal/ceramic resonator os- cillators, internal or external RC oscillator, clock security system and bypass for external clock – PLL for 2x frequency multiplication – Four Power Saving Modes: Halt, Active-Halt, Wait and Slow n Interrupt Management – Nested interrupt controller – 10 interrupt vectors plus TRAP and RESET – 9/6 external interrupt lines (on 4 vectors) n Up to 32 I/O Ports – 32/24 multifunctional bidirectional I/O lines – 22/17 alternate function lines – 12/10 high sink outputs n 4 Timers – Main Clock Controller with: Real time base, Beep and Clock-out capabilities – Configurable watchdog timer – 16

• spi - serial peripheral


• register description


• modes


• vpp pin


• asynchronous reset


• low voltage


• clock security


• characteristics


• sci interface